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1 copyright ? cirrus logic, inc. 2009 (all rights reserved) http://www.cirrus.com cs5509 single-supply, 16-bit a/d converter features ? delta-sigma a/d converter - 16-bit, no missing codes - linearity error: 0.0015%fs ? differential input - pin-selectable unipolar/bipolar ranges - common mode rejection 105 db @ dc 120 db @ 50, 60 hz ? either 5v or 3.3v digital interface ? on-chip self-calibration circuitry ? output update rate s up to 200/second ? ultra low power: 1.7 mw description the cs5509 is a single-supply, 16-bit, serial-output cmos a/d converter. the cs5509 uses charge-bal- anced (delta-sigma) techniques to provide low-cost, high-resolution measurements at output word rates up to 200 samples per second. the on-chip digital filter offe rs superior line rejection at 50hz and 60hz when the device is operated from a 32.768 khz clock (output word rate = 20 sps). the cs5509 has on-chip self-calibration circuitry which can be initiated at any time or temperature to ensure minimum offset and full-scale errors. low power, high resolution, and small package size make the cs5509 an ideal solution for loop-powered transmitters, panel meters, weigh scales, and battery powered instruments. ordering in formation CS5509-ASZ -40 c to +85 c 16-pin soic lead free i differential 4th order delta-sigma modulator vd+ 13 va+ vref+ 9 vref- 10 ain- 8 ain+ 7 calibration sram serial interface logic digital filter xin 4 xout 5 conv 2 calibration c osc cal 3 6 bp/up cs 1 drdy 16 sdata 15 sclk 14 11 gnd 12 sep ?09 ds125f3
cs5509 2 ds125f3 notes: 1. both source resistance and shunt capacitance are critical in determ ining the cs5509's source impedance requirements. refer to the text section analog input impedance considerations. 2. specifications guaranteed by design, characterization and/or test. 3. applies after calibration at the temperature of interest. 4. total drift over the specified temperature range since calibration at power-up at 25 c. 5. the input is different ial. therefore, gnd signal + common mode voltage va+. 6. the cs5509 can accept input voltages up to the va+ analog supply. in unip olar mode the cs5509 will output all 1's if the dc input ma gnitude ((ain+) - (ain-)) exceeds (( vref+) - (vref-)) and will output all 0's if the input becomes more negative than 0 volts. in bipolar mode the cs5509 will output all 1's if the dc input magnitude ((ain+) - (ain-) ) exceeds ((vref+) - (v ref-)) and will output all 0's if the input becomes more negative in magnitude than -((vref+) - (vref-)). 7. all outputs unloaded. a ll inputs cmos levels. * refer to the specification definitions imme diately following the pin description section. analog characteristics (t a = 25 c; va+ = 5v 5%; vd+ = 3.3v 5%; vref+ = 2.5v, vref- = 0v; f clk = 32.768 khz; bipolar mode; r source = 40 with a 10 nf to gnd at ain; ain- = 2.5v; unless oth- erwise specified.) (notes 1 and 2) parameter* min typ max unit accuracy linearity error f clk = 32.768 khz f clk = 165 khz f clk = 247.5 khz f clk = 330 khz - - - - 0.0015 0.0015 0.0015 0.005 0.003 0.003 0.003 0.0125 %fs %fs %fs %fs differential nonlinea rity - 0.25 0.5 lsb full-scale error (note 3) - 0.25 2 lsb full-scale drift (note 4) - 0.5 - lsb unipolar offset (note 3) - 0.5 2 lsb unipolar offset drift (note 4) - 0.5 - lsb bipolar offset (note 3) - 0.25 1 lsb bipolar offset drift (note 4) - 0.25 - lsb noise (referred to output) - 0.16 - lsb rms analog input analog input range unipolar bipolar (notes 5 and 6) - - 0 to +2.5 2.5 - - v v common mode rejection dc f clk = 32.768 khz 50, 60 hz (note 2) - 120 105 - - - db db input capacitance - 15 - pf dc bias current (note 1) - 5 - na power supplies dc power supply currents i to ta l i analog i digital - - - 350 300 60 450 - - a a a power dissipation (note 7) - 1.7 2.25 mw power supply rejection - 80 - db
cs5509 ds125f3 3 notes: 8. all measurements are performed under static conditions. 9. i out = -100 a. this guar antees the ability to dr ive one ttl load. (v oh = 2.4 v at i out = -40 a). specifications are subjec t to change without notice dynamic characteristics parameter symbol ratio unit modulator sampling frequency f s f clk /2 hz output update rate (conv = 1) f out f clk /1622 hz filter corner frequency f -3db f clk /1928 hz settling time to 1/2 lsb (fs step) t s 1/f out s 5v digital characteristics (t a = 25 c; va+, vd+ = 5v 5%; gnd = 0) (notes 2 and 8) parameter symbol min typ max unit high-level input voltage xin all pins except xin v ih 3.5 2.0 - - - - v v low-level input voltage xin all pins except xin v il - - - - 1.5 0.8 v v high-level output voltage (note 9) v oh (vd+) -1.0 - - v low-level output voiltage i out = 1.6 ma v ol --0.4v input leakage current i in -110a 3-state leakage current i oz --10a digital output pin capacitance c out -9-pf 3.3v digital characteristics (t a = 25 c; va+ = 5v 5%; vd+ = 3.3v 5%; gnd = 0) (notes 2 and 8) parameter symbol min typ max unit high-level input voltage xin all pins except xin v ih 0.7 vd+ 0.6 vd+ - - - - v v low-level input voltage xin all pins except xin v il - - - - 0.3 vd+ 0.16 vd+ v v high-level output voltage (note 9) v oh (vd+) -0.3 - - v low-level output voltage i out = 1.6 ma v ol --0.3v input leakage current i in -110a 3-state leakage current i oz --10a digital output pin capacitance c out -9-pf
cs5509 4 ds125f3 notes: 10. specified using 10% and 90% points on waveform of interest. 11. an internal power-on-reset is activated whenever power is applied to the device. 12. oscillator start-up time varies wit h the crystal parameters. this specif ication does not apply when using an external clock source. 13. the wake-up period begins once the oscillator starts; or when using an external f clk , after the power-on reset time elapses. 14. calibration can also be initiated by pulsing cal high while conv=1. 15. conversion time will be 1622/f clk if conv remains high continuously. 5v switching c haracteristics (t a = 25 c; va+, vd+ = 5v 5%; input levels: logic 0 = 0v, logic 1 = vd+; c l = 50 pf) (note 2) parameter symbol min typ max unit master clock frequenc y internal oscillator external clock xin f clk 30.0 30 32.768 - 53.0 330 khz khz master clock duty cycle 40 - 60 % rise times any digital input (note 10) any digital output t rise - - - 50 1.0 - s ns fall time any digital input (note 10) any digital output t fall - - - 20 1.0 - s ns start-up power-on reset period (note 11) t res -10-ms oscillator start-up time xtal = 32.768 khz (note 12) t osu -500-ms wake-up period (note 13) t wup - 1800/f clk -s calibration conv pulse width (cal = 1) (note 14) t ccw 100 - - ns conv and cal high to start of calibration t scl -- 2/f clk +200 ns start of calibration to end of calibration t cal - 3246/f clk -s conversion conv pulse width t cpw 100 - - ns conv high to start of conversion t scn -- 2/f clk +200 ns set up time bp/up stable prior to drdy falling t bus 82/f clk --s hold time bp/up stable after drdy falls t buh 0- -ns start of conversion to en d of conversion (note 15) t con - 1624/f clk -s
cs5509 ds125f3 5 3.3v switching characteristics (t a = 25 c; va+ = 5v 5%; vd+ = 3.3v 5%; input levels: logic 0 = 0v, logic 1 = vd+; c l = 50 pf) (note 2) parameter symbol min typ max unit master clock frequenc y internal oscillator external clock xin f clk 30.0 30 32.768 - 53.0 330 khz khz master clock duty cycle 40 - 60 % rise times any digital input (note 10) any digital output t rise - - - 50 1.0 - s ns fall time any digital input (note 10) any digital output t fall - - - 20 1.0 - s ns start-up power-on reset period (note 11) t res -10-ms oscillator start-up time xtal = 32.768 khz (note 12) t osu -500-ms wake-up period (note 13) t wup - 1800/f clk -s calibration conv pulse width (cal = 1) (note 14) t ccw 100 - - ns conv and cal high to start of calibration t scl -- 2/f clk +200 ns start of calibration to end of calibration t cal - 3246/f clk -s conversion conv pulse width t cpw 100 - - ns conv high to start of conversion t scn -- 2/f clk +200 ns set up time bp/up stable prior to drdy falling t bus 82/f clk --s hold time bp/up stable after drdy falls t buh 0- -ns start of conversion to en d of conversion (note 15) t con - 1624/f clk -s
cs5509 6 ds125f3 t ccw xin calibration standby standby t scl t cal xin/2 state cal conv figure 1. calibration timing (not to scale) xin xin/2 t buh conversion standby standby conv state t scn t con drdy bp/up t bus t cpw figure 2. conversion timing (not to scale)
cs5509 ds125f3 7 notes: 16. if cs is activated asynchronously to drdy , cs will not be recognized if it occurs when drdy is high for 2 clock cycles. the propagation delay time may be as great as 2 f clk cycles plus 200 ns. to guarantee proper clocking of sdata when using asynchronous cs , sclk(i) should not be taken high sooner than 2 f clk + 200 ns after cs goes low. 17. sdata transitions on the falling edge of sclk. note th at a rising sclk must occur to enable the serial port shifting mechani sm before falling edges can be recognized. 18. if cs is returned high before all dat a bits are output, the sdata outp ut will complete th e current data bit and then go to high impedance. 5v switching c haracteristics (t a = 25 c; va+, vd+ = 5v 5%; input levels: logic 0 = 0v, logic 1 = vd+; c l = 50 pf) (note 2) parameter symbol min typ max unit serial clock f sclk 0-2.5mhz serial clock pulse width high pulse width low t ph t pl 200 200 - - - - ns ns access time cs low to data valid (note 16) t csd -60200ns maximum delay time (note 17) sclk falling to new sdata bit t dd -150310ns output float delay cs high to output hi-z (note 18) sclk falling to hi-z t fd1 t fd2 - - 60 160 150 300 ns ns 3.3v switching characteristics (t a = 25 c; va+ = 5v 5%; vd+ = 3.3v 5%; input levels: logic 0 = 0v, logic 1 = vd+; c l = 50 pf) (note 2) parameter symbol min typ max unit serial clock f sclk 0 - 1.25 mhz serial clock pulse width high pulse width low t ph t pl 200 200 - - - - ns ns access time cs low to data valid (note 16) t csd -100200ns maximum delay time (note 17) sclk falling to new sdata bit t dd -400600ns output float delay cs high to output hi-z (note 18) sclk falling to hi-z t fd1 t fd2 - - 70 320 150 500 ns ns
cs5509 8 ds125f3 sclk(i) msb-1 msb msb-2 sdata(o) hi-z msb-1 msb lsb+2 lsb+1 lsb sclk(i) sdata(o) hi-z t fd1 t csd t dd t ph t pl t dd t csd cs cs drdy drdy t fd2 figure 3. timing relationships (not to scale)
cs5509 ds125f3 9 notes: 19. all voltages with respect to ground. 20. the cs5509 can be operated with a reference voltage as low as 100 mv; but with a corresponding reduction in noise-free resolution. the common mode voltage of the voltage reference may be any value as long as +vref and -vref remain insi de the supply values of va+ and gnd. notes: 21. no pin should go more positive than (va+) + 0.3 v. 22. vd+ must always be less than (va+) + 0.3 v, and can never exceed +6.0 v. 23. applies to all pins including continuous overvo ltage conditions at the analog input (ain) pin. 24. transient currents of up to 100 ma will not caus e scr latch-up. maximum in put current for a power supply pin is 50 ma. 25. total power dissipation, including all input currents and output currents. *warning:operation at or beyond these limits ma y result in permanent damage to the device. normal operation is not gu aranteed at these extremes. recommended operating conditions (dgnd = 0v) (note 19) parameter symbol min typ max unit dc power supplies positive digital positive analog vd+ va+ 3.15 4.75 5.0 5.0 5.5 5.5 v v analog reference voltage (note 20) (vref+) - (vref-) 1.0 2.5 3.6 v analog input voltage (note 6) unipolar bipolar vain vain 0 -((vref+) - (vref-)) - - (vref+) - (vref-) (vref+) - (vref-) v v absolute maximum ratings* parameter symbol min typ max unit dc power supplies ground (note 21) positive digital (note 22) positive analog gnd vd+ va+ -0.3 -0.3 -0.3 - - - (vd+)-0.3 6.0 6.0 v v v input current, any pin except supplies (notes 23 and 24) i in --10ma output current i out --25ma power dissipation (total) (note 25) - - 500 mw analog input voltage ain and vref pins v ina -0.3 - (va+)+0.3 v digital input voltage v ind -0.3 - (vd+)+0.3 v ambient operating temperature t a -40 - 85 c storage temperature t stg -65 - 150 c
cs5509 10 ds125f3 general description the cs5509 is a low power, 16-bit, monolithic cmos a/d converter desi gned specifically for measurement of dc signa ls. the cs5509 includes a delta-sigma charge-balan ce converter, a voltage reference, a calibration microcontroller with sram, a digital filter and a serial interface. the cs5509 is optimized to operate from a 32.768 khz crystal but can be driv en by an external clock whose frequency is between 30khz and 330khz. when the digital filter is operated with a 32.768 khz clock, the filter has zeros precisely at 50 and 60 hz line frequencies and multiples thereof. the cs5509 uses a "start convert" command to start a convolution cycle on the digital filter. once the filter cycle is comple ted, the output port is up- dated.when operated wi th a 32.768khz clock the adc converts and updates its output port at 20 samples/sec.the output por t operates in a synchro- nous externally-clocked interface format. theory of operation basic converter operation the cs5509 a/d converter has three operating states. these are stand-by, calibration, and conver- sion. when power is first applied, an internal pow- er-on reset delay of about 10 ms resets all of the logic in the device. the os cillator must then begin oscillating before the device can be considered functional. after the power-on reset is applied, the device enters the wake-up period for 1800 clock cycles after clock is presen t. this allows the delta- sigma modulator and other circuitry (which are op- erating with very low cu rrents) to reach a stable bias condition prior to entering into either the cali- bration or conversion stat es. during the 1800 cycle wake-up period, the device can accept an input command. execution of this command will not oc- cur until the complete wa ke-up period elapses. if no command is given, the de vice enters the standby state. calibration after the initial applic ation of power, the cs5509 must enter the calibration state prior to performing accurate conversions. du ring calibration, the chip executes a two-step proces s. the device first per- forms an offset calibrati on and then follows this with a gain calibration. the two calibration steps determine the zero reference point and the full scale reference point of the conve rter's transfer function. from these points it calibr ates the zero point and a gain slope to be used to properly scale the output digital codes when doing conversions. the calibration state is en tered whenever the cal and conv pins are high at the same time. the state of the cal and conv pins at power-on are recog- nized as commands, but will not be executed until the end of the 1800 cloc k cycle wake-up period. if cal and conv become active (high) during the 1800 clock cycle wake-up ti me, the converter will wait until the wake-up pe riod elapses before exe- cuting the calibration. if the wake-up time has elapsed, the converter wi ll be in the standby mode waiting for instruction and will enter the calibration cycle immediately if cal and conv become ac- tive. the calibration last s for 3246 clock cycles. calibration coefficients are then retained in the sram (static ram) for use during conversion. the state of bp/up is ignored during calibration but should remain stable throughout the calibration period to minimize noise. when conversions are pe rformed in unipolar mode or in bipolar mode, the c onverter uses the same cal- ibration factors to comput e the digital output code. the only difference is that in bipolar mode the on- chip microcontroller o ffsets the computed output word by a code value of 80 00h. this means that the bipolar measurement range is not calibrated from full scale positive to full s cale negative. instead it is calibrated from the bipolar zero scale point to full scale positive. the slope factor is then extended be- low bipolar zero to accom modate the negative in-
cs5509 ds125f3 11 put signals. the converter can be used to convert both unipolar and bipolar signals by changing the bp/up pin. recalibration is not required when switching between unipolar and bipolar modes. at the end of the calibrati on cycle, the on-chip mi- crocontroller checks the logic state of the conv signal. if the conv input is low the device will en- ter the standby mode where it waits for further in- struction. if the conv sign al is high at the end of the calibration cycle, the converter will enter the conversion state and perf orm a conversion on the input channel. the cal signal can be returned low any time after calibrati on is initiated. conv can also be returned low, but it should never be taken low and then taken back high until the calibration period has ended and the c onverter is in the standby state. if conv is taken low and then high again with cal high while the converter is calibrating, the device will interrupt the current calibration cy- cle and start a new one. if cal is taken low and conv is taken low and then high during calibra- tion, the calibration cycle w ill continue as the con- version command is disregarded. the state of bp/up is not important during calibrations. if an "end of calibration" si gnal is desired, pulse the cal signal high while l eaving the conv signal high continuously. once the calibration is complet- ed, a conversion wi ll be performe d. at the end of the conversion, drdy will fall to indicate the first valid conversion after th e calibration has been completed. conversion the conversion state can be entered at the end of the calibration cycle, or whenever the converter is idle in the standby mode . if conv is taken high to initiate a calibration cycl e ( cal also high), and re- mains high until the calibr ation cycle is completed (cal is taken low after conv transitions high), the converter will begi n a conversion upon comple- tion of the calibration period. the bp/up pin is not a latc hed input. the bp/up pin controls how the output word from the digital filter is processed. in bi polar mode the output word computed by the digital filter is offset by 8000h (see understanding converter calibration). bp/up can be changed after a conve rsion is started as long as it is stable for 82 cloc k cycles of the conversion period prior to drdy falling. if one wishes to in- termix measurement of bi polar and unipolar signals on various input signals, it is best to switch the bp/up pin immediately after drdy falls and leave bp/up stable until drdy falls again. the digital filter in the cs5509 has a finite im- pulse response and is designe d to settle to full ac- curacy in one conversion time. if conv is left high, the cs5509 will perform con- tinuous conversions. the conversion time will be 1622 clock cycles. if conve rsion is initiated from the standby state, there ma y be up to two xin clock cycles of uncertainty as to when conversion actual- ly begins. this is because the internal logic oper- ates at one half the extern al clock rate and the exact phase of the internal clock may be 180 out of phase relative to the xi n clock. when a new con- version is initia ted from the standby state, it will take up to two xin clock cycles to begin. actual conversion will use 1624 clock cycles before drdy goes low to indicate that the serial port has been updated. see the seri al interface logic sec- tion of the data sheet for information on reading data from the serial port. in the event the a/d c onversion command (conv going positive) is issued during the conversion state, the current conversi on will be terminated and a new conversion will be initiated. voltage reference the cs5509 uses a differen tial voltage reference input. the positive input is vref+ and the nega- tive input is vref-. th e voltage between vref+ and vref- can range from 1 volt minimum to 3.6 volts maximum. the gain slope will track changes
cs5509 12 ds125f3 in the reference without recalibration, accommo- dating ratiometric applications. analog input range the analog input range is set by the magnitude of the voltage between the vref+ and vref- pins. in unipolar mode the input range will equal the magnitude of the voltage reference. in bipolar mode the input voltage ra nge will equate to plus and minus the magnitude of the voltage reference. while the voltage referenc e can be as great as 3.6 volts, its common mode voltage can be any value as long as the reference inputs vref+ and vref- stay within the supply voltages va+ and gnd. the differential input vo ltage can also have any common mode valu e as long as the maximum sig- nal magnitude stays within the supply voltages. the a/d converter is intende d to measure dc or low frequency inputs. it is designed to yield accurate conversions even with noise exceeding the input voltage range as long as the spectral components of this noise will be filtered out by the digital filter. for example, with a 3.0 volt reference in unipolar mode, the converter will accurately convert an in- put dc signal up to 3.0volts with up to 15% over- range for 60hz noise. a 3.0volt dc signal could have a 60hz componen t which is 0.5volts above the maximum input of 3.0 (3.5 volts peak; 3.0 volts dc plus 0.5 volts peak noise) and still accurately convert the input signal (xin = 32.768 khz). this assumes that the signal pl us noise amplitude stays within the supply voltages. the cs5509 converters output data in binary for- mat when converting unipolar signals and in offset binary format when conve rting bipolar signals. ta- ble 1 outlines the output coding for both unipolar and bipolar measurement modes. converter performance the cs5509 a/d converter has excellent linearity performance. calibration minimizes the errors in offset and gain. the cs 5509 device has no missing code performance to 16-bits . figure4 illustrates the dnl of the cs5509. the converter achieves com- mon mode rejection (cmr ) at dc of 105db typi- cal, and cmr at 50 and 60hz of 120db typical. the cs5509 can experience some drift as tempera- ture changes. the cs5509 uses chopper-stabilized techniques to minimize drift. measurement errors due to offset or gain drif t can be eliminated at any time by recalibra ting the converter. analog input impedance considerations the analog input of the cs5509 can be modeled as illustrated in figure 5. ca pacitors (15 pf each) are used to dynamically sample each of the inputs (ain+ and ain-). every ha lf xin cycle the switch alternately connects the cap acitor to the output of the buffer and then directly to the ain pin. when- ever the sample capacitor is switched from the out- put of the buffer to the ain pin, a small packet of charge (a dynamic demand of current) is required from the input source to se ttle the voltage of the sample capacitor to its final value. the voltage on the output of the buffer may differ up to 100 mv from the actual input voltage due to the offset volt- age of the buffer. timing allows one half of a xin clock cycle for the voltage on the sample capacitor to settle to its final value. unipolar input voltage output codes bipolar input voltage > (vref - 1.5 lsb) ffff > (vref - 1.5 lsb) vref - 1.5 lsb vref - 1.5 lsb vref/2 - 0.5 lsb -0.5 lsb +0.5 lsb -vref + 0.5 lsb < (+0.5 lsb) 0000 < (-vref + 0.5 lsb) note: table excludes common mode voltage on the signal and reference inputs. table 1. output coding ffff fffe --------------- - 8000 7fff -------------- - 0001 0000 ------------ -
cs5509 ds125f3 13 an equation for the maximum acceptable source resistance is derived. this equation assumes that the offset voltage of the buffer is 100 mv, which is the worst case. the val- ue of ve is the maximum error voltage which is ac- ceptable. c ext is the combination of any external or stray capacitance. for a maximum error voltage (ve) of 10 v in the cs5509 (1/4lsb at 16-bits), the above equation in- dicates that when operating from a 32.768 khz xin, source resistances up to 110 k are accept- able in the absence of external capacitance (c ext =0). the vref+ and vref- inputs have nearly the same structure as the ain+ and ain- inputs. therefore, the discussion on analog input imped- ance applies to the voltage reference inputs as well. digital filter characteristics the digital filter in the cs5509 is the combination of a comb filter and a low pass filter. the comb fil- ter has zeros in its transfer function which are opti- mally placed to reject line interference frequencies (50 and 60 hz and their multiples) when the cs5509 is clocked at 32.768 khz. figures 6, 7 and 8 illustrate the magnitude and phase characteristics of the filter. figure 6 illu strates the filter attenua- tion from dc to 260 hz. at exactly 50, 60, 100, and 120 hz the filter provides over 120 db of rejection. table 2 indicates the filt er attenuation for each of the potential line interfer ence frequencies when the converter is operating with a 32.768 khz clock. the converter yields excell ent attenuation of these interference frequencies even if the fundamental line frequency should vary 1% from its specified frequency. the -3 db corner frequency of the filter when operating from a 32.768 khz clock is 17 hz. figure 8 illustrates that th e phase characteristics of the filter are precisely linear phase. if the cs5509 is operated at a clock rate other than 32.768khz, the filter charact eristics, including the comb filter zeros, will scale with the operating clock frequency. therefor e, optimum rejection of figure 4. cs5509 differe ntial nonlinearity plot + 15 pf v os 100 mv + v os 100 mv internal bias voltage 15 pf ain+ ain- - - figure 5. analog input model rs max 1 ? 2xin 15pf c ext + () v e v e 15pf 100mv () 15pf c ext + ------------------------------------- + --------------------------------------------------- ln ------------------------------------------------------------------------------------------------------------------------- =
cs5509 14 ds125f3 line frequency interference will occur with the cs5509 running at 32.768khz. table 2. filter notch attenuation (xin = 32.768 khz) anti-alias considerations for spectral measurement applications input frequencies greater than one half the output word rate (conv = 1) ma y be aliased by the con- verter. to prevent this, i nput signals should be lim- ited in frequenc y to no greater than one half the output word rate of th e converter (when conv =1). frequencies close to the modulator sample rate (xin/2) and multiples ther eof may also be aliased. if the signal source in cludes spectral components above one half the output word rate (when conv = 1) these components should be removed by means of low-pass filtering prior to the a/d input 0 0 40 402.83 80 805.66 120 1208.5 160 1611.3 200 2014.2 240 2416.9 frequency (hz) -160 -140 -120 -100 -80 -60 -40 -20 0 attenuation (db) xin = 32.768 khz x1 x2 x1 = 32.768khz x2 = 330.00khz figure 6. filter magnitude plot to 260 hz 0 5 10 15 20 25 30 35 40 45 50 frequency (hz) -140 -120 -100 -80 -60 -40 -20 0 attenuation (db) flatness db -0.010 -0.041 -0.093 -0.166 -0.259 -0.510 -0.667 -0.846 -1.047 -3.093 1 2 3 4 5 6 7 8 9 10 17 xin = 32.768 khz frequency -0.374 figure 7. filter magnitude plot to 50 hz frequency (hz) notch depth (db) frequency (hz) minimum attenuation (db) 50 125.6 50 1% 55.5 60 126.7 60 1% 58.4 100 145.7 100 1% 62.2 120 136.0 120 1% 68.4 150 118.4 150 1% 74.9 180 132.9 180 1% 87.9 200 102.5 200 1% 94.0 240 108.4 240 1% 104.4 05 10 15 20 25 30 35 40 45 50 frequency (hz) -180 -135 -90 -45 0 45 90 135 180 phase (degrees) xin = 32.768 khz figure 8. filter phase plot to 50 hz
cs5509 ds125f3 15 to prevent aliasing. spec tral components greater than one half the output word rate on the vref in- puts (vref+ and vref-) ma y also be aliased. fil- tering of the reference voltage to remove these spectral components from the reference voltage is desirable. crystal oscillator the cs5509 is designed to be operated using a 32.768khz "tuning fork" type crystal. one end of the crystal should be conne cted to the xin input. the other end should be attached to xout. short lead lengths should be us ed to minimize stray ca- pacitance. over the industrial te mperature range (-40 to +85 c) the on-chip gate oscillator will oscillate with other crystals in th e range of 30khz to 53 khz. the chip will operate with external clock frequen- cies from 30khz to 330khz over the industrial tem- perature range. the 32.768 kh z crystal is normally specified as a time-keeping crystal with tight spec- ifications for both initia l frequency and for drift over temperature. to main tain excellent frequency stability, these crystals ar e specified only over lim- ited operating temperatur e ranges (i.e. -10 c to +60 c) by the manufactur ers. applications of these crystals with the cs5509 does not require tight initial tolerance or low tempco drift. there- fore, a lower cost crystal with looser initial toler- ance and tempco will genera lly be adequate for use with the cs5509. also ch eck with the manufactur- er about wide temperat ure range a pplication of their standard crystals. ge nerally, even those crys- tals specified for limited temperature range will op- erate over much larger ra nges if frequency stability over temperature is not a requirement. the frequen- cy stability can be as bad as 3000 ppm over the operating temperature range and still be typically better than the line freque ncy (50 hz or 60hz) sta- bility over cycle-to-cycle during the course of a day. serial interface logic the digital filter in th e cs5509 takes 1624 clock cycles to compute an output word once a conver- sion begins. at the end of the conversion cycle, the filter will atte mpt to update the serial port. two clock cycles prior to the update drdy will go high. when drdy goes high just prior to a port up- date it checks to see if the port is either empty or unselected (cs = 1). if the port is empty or unse- lected, the digital filter will update the port with a new output word. when new data is put into the port drdy will go low. reading serial data sdata is the output pin for the serial data. when cs goes low after new data becomes available (drdy goes low), the sdata pin comes out of hi-z with the msb data bit present. sclk is the input pin for the serial cl ock. if the msb data bit is on the sdata pin, the firs t rising edge of sclk enables the shifting mechanism. this allows the falling edges of sclk to shift subsequent data bits out of the port. note that if the msb data bit is out- put and the sclk signal is high, the first falling edge of sclk will be i gnored because the shifting mechanism has not become activated. after the first rising edge of sclk , each subsequent falling edge will shift out the se rial data. once the lsb is present, the falling edge of sclk will cause the sdata output to go to hi-z and drdy to return high. the serial port register will be updated with a new data word upon the completion of another con- version if the serial port ha s been emptied, or if the cs is inactive (high). cs can be operated async hronously to the drdy signal. the drdy signal need not be monitored as long as the cs signal is taken low for at least two xin clock cycles plus 200ns prior to sclk being toggled. this ensures that cs has gained control over the serial port.
cs5509 16 ds125f3 power supplies and grounding the analog and digital supply pins to the cs5509 are brought out on separate pins to minimize noise coupling between the analog and digital sections of the chip. in the digital section of the chip the supply current flows into the vd+ pin and out of the gnd pin. as a cmos device , the cs5509 requires that the supply voltage on the va+ pin always be more positive than the voltage on any other pin of the de- vice. if this requirement is not met, the device can latch-up or be damaged. in all circumstances the va+ voltage must remain more positive than the vd+ or gnd pins; vd+ mu st remain more posi- tive than the gnd pin. figure 9a illustrates th e system connection dia- gram for the cs5509. note th at all supply pins are bypassed with 0.1 f capacitors and that the vd+ digital supply is derived from the va+ supply. fig- ure 9b illustrates the cs 5509 operating from a +5v analog supply and +3.3v digital supply. when using separate supplies for va+ and vd+, va+ must be established first. vd+ should never become more positive th an va+ under any operat- ing condition. remember to investigate transient power-up conditions, when one power supply may have a faster rise time.
cs5509 ds125f3 17 figure 9a. system connection diagram using a single supply cs5509 +5v analog supply vd+ va+ vref+ vref- gnd 0.1 f 0.1 f 8 7 9 10 11 12 13 + - analog signal ain+ ain- sclk sdata 14 15 xin xout 16 drdy cal 3 1 cs conv 2 6 bp/up 4 5 32.768 khz 10 voltage reference optional clock source serial data interface control logic
cs5509 18 ds125f3 figure 9b. system connection diagram using split supplies cs5509 +5v analog supply vd+ va+ vref+ vref- gnd 0.1 f 0.1 f 8 7 9 10 11 12 13 + - analog signal ain+ ain- sclk sdata 14 15 xin xout 16 drdy cal 3 1 cs conv 2 6 bp/up 4 5 32.768 khz voltage reference optional clock source serial data interface control logic +3.3v to +5v digital supply note: vd+ must never be more positive than va+
cs5509 ds125f3 19 pin descriptions* * pinout applies to both pdip and soic clock generator xin; xout - crystal in; crystal out, pins 4, 5. a gate inside the chip is connect ed to these pins and can be used with a crystal to provide the master clock for the device. alternatively, an external (cmos compatible) clock can be supplied into the xin pin to provide the master clock for the device. loss of clock will put the device into a lower powered state (a pproximately 70% power reduction). serial output i/o cs - chip select, pin 1. this input allows an external device to access the serial port. drdy - data ready, pin 16. data ready goes low at the end of a digital filter convolution cycle to indicate that a new output word has been placed into the serial port. drdy will return high af ter all data bits are shifted out of the serial port or two master clock cycles before new data becomes available if the cs pin is inactive (high). sdata - serial data output, pin 15. sdata is the output pin of the se rial output port. data from th is pin will be output at a rate determined by sclk. data is output msb first and advances to th e next data bit on the falling edges of sclk. sdata will be in a high im pedance state when not transmitting data. sclk - serial clock input, pin 14. a clock signal on this pin determin es the output rate of the data from the sdata pin. this pin must not be allowed to float. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 drdy sdata sclk vd+ gnd va+ vref- vref+ ain- ain+ bp/up xout xin cal conv cs differential analog input differential analog input bipolar / unipolar crystal out crystal in calibrate convert chip select data ready serial data output serial clock input positive digital power ground positive analog power voltage reference input voltage reference input
cs5509 20 ds125f3 control input pins cal - calibrate, pin 3. when taken high the same time that the conv pin is taken high the c onverter will perform a self-calibration which includes cali bration of the offset and gain scale factors in the converter. conv - convert, pin 2. the conv pin initiates a calibrati on cycle if it is ta ken from low to high while the cal pin is high, or it initiates a conversion if it is taken from low to high with the cal pin low. if conv is held high (cal low) the convert er will do continuous conversions. bp/up - bipolar/unipolar, pin 6. the bp/up pin selects the conversion mode of th e converter. when high the converter will convert bipolar input signals; when low it will convert unipolar input signals. measurement and reference inputs ain+, ain- - differential analog inputs, pins 7, 8. analog differential inputs to the delta-sigma modulator. vref+, vref- - differential volt age reference inputs, pins 9, 10. a differential voltage referenc e on these pins operates as the voltage reference for the converter. the voltage between these pins can be any voltage between 1.0 and 3.6 volts. power supply connections va+ - positive analog power, pin 11. positive analog supply volta ge. nominally +5 volts. vd+ - positive digital power, pin 13. positive digital supply voltage. no minally +5 volts or +3.3 volts. gnd - ground, pin 12. ground.
cs5509 ds125f3 21 specification definitions linearity error the deviation of a code from a straight line which connect s the two endpoints of the a/d converter transfer function. one endpoint is located 1/2 lsb belo w the first code transition and the other endpoint is located 1/ 2 lsb beyond the code transition to all ones. units in percent of full-scale. differential nonlinearity the deviation of a code's width fr om the ideal width. units in lsbs. full scale error the deviation of the last code transition from the ideal [{(vref+) - (v ref-)} - lsb]. units are in lsbs. unipolar offset the deviation of the first code transition fro m the ideal ( lsb above the voltage on the ain- pin.) when in unipolar mode (bp/up low). units are in lsbs. bipolar offset the deviation of the mid-scale transition (0 11...111 to 100...000) from the ideal ( lsb below the voltage on the ain- pin.) when in bipolar mode (bp/up high). units are in lsbs
cs5509 22 ds125f3 package dimensions soic millimeters inches min max max min 0.095 0.105 2.41 2.67 0.008 0.015 0.203 0.381 0.398 0.420 10.11 10.67 0.020 0.013 0.51 0.33 0.016 0.035 0.41 0.89 8 0 0 8 millimeters inches min max max min pins 0.410 0.390 9.91 10.41 16 0.510 0.490 12.45 12.95 20 0.610 0.590 14.99 15.50 24 0.710 0.690 17.53 18.03 28 0.012 0.005 0.127 0.300 1.14 0.040 dim e e b l d e a a c 0.292 0.298 7.42 7.57 d e e 1 e a a b 1 a 2 c l 1 1 1.40 0.055 a 2 see table above nom 2.54 0.280 10.41 0.46 - - nom 10.16 12.70 15.24 17.78 - 7.49 1.27 2.29 2.54 2.41 nom 0.100 0.011 0.410 0.018 - - nom 0.400 0.500 0.600 0.700 - 0.295 0.050 0.100 0.090 0.095
cs5509 ds125f3 23 environmental, manufactur ing, & handling information * msl (moisture sensitivity level) as specified by ipc/jedec j-std-020. model peak relfow temp msl rating* maximum floor life CS5509-ASZ (lead free) 260 c 3 7 days
cs5509 24 ds125f3 revision history revision date changes f1 aug ?97 first ?final? release. f2 aug ?05 added lead-free device ordering info. added legal notice. added msl data. f3 jul ?09 removed pdip and leaded (pb) devices from ordering information. contacting cirrus logic support for all product questions an d inquiries contact a cirrus logic sales representative. to find the one nearest to you go to www.cirrus.com important notice cirrus logic, inc. and its subsidiaries (?cirrus?) believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided ?as is? without warranty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pe rtaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishi ng this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe prop- erty or environmental damage (?critical applications?). cirru s products are not designed, authorized or warranted for use in products surgically implante d into the body, au tomotive safety or secur ity devices, life support products or other crit- ical applications. inclusion of cirrus products in such applications is unde rstood to be fully at the customer's risk and cirrus disclaims and makes no wa rranty, express, statut ory or implied, including the im plied warranties of merchantability and fitness for particular purp ose, with regard to any cirrus product that is used in such a manner. if the customer or customer's customer uses or permits the use of cirrus products in critical applications, custo mer agrees, by such use, to fully indemnify cirrus, its officers, directors, employees, distributors and other agents from any and all liability, includ- ing attorneys' fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners.

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